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Ordering number : EN5429A
Wideband Output Module (Video Pack)
VP301
Ultrahigh Resolution CRT Display Video Output Amplifier
Features
* Ultrahigh frequency, wide bandwidth video output f (-3 dB) = 145 MHz, VO = 40 to 50 Vp-p * Molded construction (9 pins) * Optimal for monitors that require an fH greater than 90 kHz
Package Dimensions
unit: mm
2136
[VP301]
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Maximum supply voltage Allowable power dissipation Junction temperature Case temperature Storage temperature Symbol VCC max VBB max Pd max Tj max Tc Tstg Ideal heat sink at Ta = 25C Conditions Ratings 90 15 25 150 100 -20 to +110 Unit V V W C C C
Operating Conditions at Ta = 25C
Parameter Recommended supply voltage I Symbol VCC VBB VCC VBB Conditions Ratings 70 10 80 10 Unit V V V V
Recommended supply voltage II
Electrical Characteristics at Ta = 25C
Parameter Frequency band I (-3 dB) Frequency band II (-3 dB) Impulse response characteristics Voltage gain Symbol fc fc tr tf GV (DC) ICC (1) Current drain I ICC (2) ICC (1) Current drain II ICC (2) VCC = 70 V, VBB = 10 V, VIN (DC) = 2.7 V, f = 10 MHz clock, CL = 5 pF, VOUT (p-p) = 40 V VCC = 70 V, VBB = 10 V, VIN (DC) = 2.7 V, f = 150 MHz clock, CL = 5 pF, VOUT (p-p) = 40 V VCC = 80 V, VBB = 10 V, VIN (DC) = 3.0 V, f = 10 MHz clock, CL = 5 pF, VOUT (p-p) = 50 V VCC = 80 V, VBB = 10 V, VIN (DC) = 3.0 V, f = 150 MHz clock, CL = 5 pF, VOUT (p-p) = 50 V Conditions VCC = 70 V, VBB = 10 V, CL = 5 pF, VIN (DC) = 3.0 V, VOUT (p-p) = 40 V VCC = 80 V, VBB = 10 V, CL = 5 pF, VIN (DC) = 3.3 V, VOUT (p-p) = 50 V VCC = 80 V, VBB = 10 V, CL = 5 pF, VIN (DC) = 3.3 V, VOUT (p-p) = 40 V 13 Ratings min typ 145 140 3.0 2.4 15 65 95 76 105 17 max Unit MHz MHz ns ns double mA mA mA mA
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N3096HA (OT) No. 5429-1/6
VP301 IC Peripheral Circuit (output block) Application Example
Matching RC circuit .......This RC circuit matches the video pack output to the transmission system. It is not required if
the total output capacitance Co(total) is no more than 15 pF.
ROUT ...............................Determine the value of this resistor based on the discharge test withstand capacity and the
required frequency bandwidth.
Internal Equivalent Circuit
VP301 Test Circuit
No. 5429-2/6
VP301
No. 5429-3/6
VP301 Surge Protection Surge protection is required when this device is connected to a CRT. This product requires the same protection as earlier products. A. Termination spark gap B. Surge suppression resistor C. Surge suppression diode (Installed in the vicinity of the IC output pin.) Caution: The value of surge suppression resistors must be determined taking both the stipulated discharge test and the required frequency bandwidth into account. Notes on Mounting * Heat sink mounting Since the specified heat sink is required to operate a mounted video pack, we recommend the following mounting technique. (See the thermal design item for details on the required heat sink.) In particular, since the package used for this product is even more compact than that used in the earlier VPA series, the following points require special care. (These are recommendations.) 1. A tightening torque of between 39 and 58 N*cm is recommended. Note that 49 N*cm is the standard torque. 2. The bolt hole spacing in the heat sink should match that of the IC. In particular, the bolt hole spacing should be made as close as possible, within the range that mounting is possible, to the dimensions A and B in the package dimensions drawing, as shown below.
3. Use either the truss screws (truss bolts) or binding screws (binding bolts) stipulated in the JIS standards as the mounting bolts. Also, use washers to protect the IC case. 4. Foreign matter, such as machining chips, must not be left trapped between the IC case and the heat sink. If grease is applied to the junction surface, be sure to apply the grease evenly. 5. Solder the IC leads to the printed circuit board after mounting the heat sink to the IC. Note: The heat sink is absolutely required to operate this video pack. Never, in any situation, apply power to a video pack as an independent device. The video pack may be destroyed. * Peripheral wiring and ground leading * Inputs and outputs must be laid out as direct lines and must not cross. * If a double-sided printed circuit board is used, the output pattern must not be laid out on the other side of the printed circuit board from the ground pattern, since this would increase the output capacitance.
IC Peripheral Pin Layout (Top view)
No. 5429-4/6
VP301 Thermal Design During operation, the transistor junction temperature must remain under 150C, the maximum junction temperature (Tjmax) for the VP301. The following section presents thermal design data and a thermal design example for the VP301. Thermal Design for the VP301 The heat generated by the transistors in a video pack varies with the frequency, and also varies between the transistors in the video pack themselves. Here, thermal design consists of selecting a heat sink such that transistor junction temperatures in the worst case do not exceed 150C. Taking the upper limit of the operating frequency, 150 MHz (clock) as a representative usage of the VP301, we consider thermal design at this frequency. From Figure 1 we can see that transistor 3 (Tr3 in the SEPP stage) generates the largest amount of heat, and that the loss (heat generation) in this transistor is about 22% of the total loss. The chip temperature of each transistor is determined using the following formula. Tj (Tri) = j-c (Tri) x PC (Tri) + Tc + Ta [C] ...........................................Formula (1) j-c(Tri): Thermal resistance of an individual transistor* Pc(Tri): Loss for an individual transistor Tc: Case temperature rise Ta: Ambient temperature (chassis internal temperature) * For the VP301, j-c (Tr1) = 40C/W, j-c (Tr2 to Tr4) = 25C/W...........(a) Sample Calculation Thermal resistance, h, for a heat sink for use at VCC = 80 V, VBB = 10 V, VO = 50 Vp-p, f = 150 MHz (clock) at temperatures up to 60C. Considering figures 1 and 2, we focus on transistor 3 and determine the temperature. The loss in transistor 3, PC(Tr3), can be estimated using the value of Pd(total) from Figure 2 to be: PC (Tr3) = Pd (total) f = 150 MHz x PCratio (Tr3) = 8.3 x 0.22 ......................Formula (2) 1.83 [W] From formula (1) and (a) the temperature rise for the transistor, Tj(Tr3) can be calculated to be: Tj (Tr3) = j-c (Tr3) x PC (Tr3) = 25 x 1.83..............................................Formula (3) = 45.75 [C] Since Tc(max) = 100C and Tj(max) = 150C = Tj + Tc(max), it suffices to determine a thermal resistance for the heat sink so that Tc(max) does not exceed 100C. Assuming operation at an ambient temperature of Ta = 60C, the allowable case temperature rise will be: Tc = 100 - 60 = 40C. Therefore, h = Tc / Pd (total) f = 150 MHz = 40 / 8.3..............................................Formula (4) And this is: = 4.8[C/W] Note: The above calculation assumes 100% operation at the clock frequency. However, since CRT operation also includes blanking periods, clock operation can be expected to be about 80% of the time. Since video packs are operated at close to the cutoff state during blanking periods, the loss during this period can be assumed to be zero, and the total loss, Pd(total), will be: Pd (total) f = 150 MHz = Pd (total) f = 150 MHz x 0.8 = 8.3 x 0.8 = 6.64 [W] Thus the heat sink can be made smaller than the one calculated above. We recommend performing a full thermal designs based on the actual operating conditions.
No. 5429-5/6
VP301
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1996. Specifications and information herein are subject to change without notice. No. 5429-6/6

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